Analysis of Decoupling Capacitor Performance in Improving Power Integrity in Two Layer/Three Layer Printed Circuit Boards

Electronic circuits can only function properly if supplied with clean power. The clean power is only possible if the AC. & D.C. noise in the power supply voltage which is supplied to electronic devices is below tolerance limits. To keep this noise within the limits, the impedance of Power Distribution Network (PDN) should be as minimal as possible. The use of Decoupling Capacitors is the most proven strategy to keep the PDN impedance low. In this paper, an attempt has been made to analyze the performance of PDN of a two-layer and three-layer P.C. Board, for the same set of Decoupling Capacitors. The PDN design has been carried out to meet an assumed set of specifications. The values of Interconnection Inductance have been obtained. The Interconnection Inductance is mostly responsible for PDN impedance, especially at higher frequencies. The simulations have been conducted for the PDN impedance of a two-layer as well as a three-layer P.C. Board. From the simulated impedance profiles, it is evident that PDN impedance obtained for a two-layer P.C. board is almost similar to that of a three-layer one if the width of the power supply trace is suitably tailored. It is therefore more prudent to go for a two-layer PDN configuration considering its simplicity and economy.


Introduction
PCBs have been an essential part of every electronic system.The design of PCB layout has been limited only to rating of conductors and selecting their widths traditionally.
With Advent of high-speed semiconductor device, the speed of signals has increased considerably.To deliver these high-speed signals, the switching speed of Integrated Circuit has increased considerably [1].These higher switching speeds coupled with higher magnitudes of load currents, induce noise in the Power Distribution Network (PDN).
The noise in the PDN Network severely affects the magnitude and shape of signals being delivered by Integrated Circuits.The PDN noise can only be minimized by reducing the value of PDN impedance.The reduction in PDN impedance is possible by increasing the width of power distribution network conductors.But, this traditional approach can no more work at high switching speeds.The use of decoupling capacitors for every highspeed IC is the only way to reduce the PDN impedance and make it noise-free.This paper discusses the performance of Decoupling capacitors, for improving Power Integrity [2] by reducing PDN impedance by selecting the value and number of Decoupling capacitors (Decaps) for keeping the PDN impedance below the targeted value over the entire frequency spectrum of circuit operation, in two layer and three layer Printed Circuit Board Configurations.To supplement the theoretical design approach, the design has been carried out for PDN system for delivery 1 A load current and switching speeds up to 1 GHz.

Role of Decoupling Capacitors
Decoupling Capacitors (Decaps) are required to be connected to power supply pins of the semiconductor devices so as to meet instantaneous current demands thereby reducing power bus noise and hence improving the Power Integrity.Bulk capacitors play a major role in improving the performance of Power Distribution Network (PDN) at lower frequencies i.e., up to 1 MHz [3].This can be very easily done with one or two high value capacitors in parallel connection.But the high-frequency performance is the real challenging one.High-value capacitors are no longer useful due to their sluggish response, therefore small ceramic disc capacitors are required to be connected in parallel.The parallel combination of several Decaps helps in reducing ESL as well as ESR while increasing the total equivalent capacitance.

Decoupling Capacitor Parasitics and their Calculations
Equivalent series Inductance (ESL) of a Decap: 3.1.The Basis for Calculations 1) Size of GND plane; 2) Size of PWR plane; 3) Distance of Decaps from IC; 4) Thickness of dielectric (Signal to GND); 5) Thickness of dielectric between GND & Power planes; 6) Decap specifications from manufacturer.
5. Diameter of via: 0.305 mm. 6.The Decap specs: as mentioned in Table IV.[4] where h is in mm (but for single via).

Calculation for a Two-Layer Board
[8] The total Parasitic interconnection inductance of Decaps: = L vp + L via−via = 6.37 nH Thus, it is observed that Parasitic interconnection inductance of Decaps in a three-layer P.C. Board is just 0.12 nH lower than in a two-layer P.C. Board.Inductance, L ii = 6.37 nH [4].

Summary of Inductance Calculations
Inductance calculations have been summarized in Tables I-III.

Selection of Decoupling Capacitors
The following PDN Specifications were considered for the Design of PDN: V ss = 3.3 V, I max = 1 A, V ripple = 5.5%, Bandwidth (Highest frequency) = 1 GHz.Decoupling capacitors were selected for achieving the target impedance, Z T-PDN .Z T−PDN ≤ [(V ss × Ripple %)/0.5I max ] ≤ 0.363 [5], [9] PDN was designed to meet above specifications using Frequency Domain Target impedance method [10], [11].The Decaps were selected and the values of their parasitics such as ESR, ESL were obtained from manufacturer's data sheets [6], [12].These values are mentioned in Table IV.

Simulation Results
PDN Impedance Profile for a 2-Layer P.C. Board [13] with Higher Width of Conductor from Decap to I.C. for Decaps Listed in Table IV is shown in Fig. 3.
PDN Impedance Profile for a 3-Layer P.C. Board with set of Decaps Listed in Table IV is shown in Fig. 4.
PDN Impedance Profiles for a 3-Layer and 2-Layer P.C. Boards with the set of Decaps Listed in Table IV is shown in Fig. 5.

Conclusion
Power is absolutely essential for high speed printed circuit boards.It can be achieved only if the impedance of conductors which are part of the power distribution system is kept low.The low impedance of the Power Distribution Network can be realized by using decoupling capacitors of specific values and quantities.A three-layer P.C. Board has dedicated layers for power and ground planes.The impedance profile obtained for a three-layer P.C. Board for a set of values and quantity of Decoupling Capacitors has shown a maximum impedance of 0.338 , at the highest frequency of 1 GHz.Whereas a two-layer P.C. Board with one layer as a Ground plane and the other for power/signal conductors, when simulated for the same set of decoupling capacitors, the PDN impedance at 1 GHz, was found to be, 0.336 .The reduction is possible as Two two-layer configuration has a lesser number of vias than that of a Three-layer P.C. Board.It can therefore be concluded that better performance can be obtained from a PDN of a two-layer P.C. Board if the width of the power conductor is tailored beyond theoretical design values obtained for carrying the specified load current.Thus, it shall be more economical and simpler, if a twolayer P.C. Board is preferred over a three-layer, at higher frequencies, in particular.
Fig. A typical two layer board.
Total ESL of Decap system = (ESL self + Parasiticinterconnection inductance of Decaps) Parasitic interconnection inductance of Decaps = Spreading Inductance + Via Inductance ESL self varies from capacitor to capacitor.Circuit configuration (Two-layer) is depicted on Fig. 1.Parasitic interconnection inductance of Decaps: i) Via pair loop Inductance:

TABLE I :
Type of PC Board: Two Layer

TABLE II :
Type of PC Board: Three Layer Dimensions (W × L) of Ground plane in mm: 50 × 50.

TABLE III :
Type of PC Boards: Two Layer with width Power Conductor Doubled Dimensions (W × L) of Ground plane in mm: 50 × 50.