Parametric Simulation Study of Control Coefficients on the On-Off Current Ratio of Single-Walled Carbon Nanotube Field Effect Transistor

As the semiconductor business faces increasing technical and financial challenges, it is crucial to assess and analyze new ideas thoroughly. The unique properties of carbon nanotubes make them a promising material for applications in micro and nanoelectronics. The study focused on simulating the impact of control coefficients (gate and drain) on device characteristics. The simulation results were then analyzed using existing models. This research focused on studying the ION/IOFF ratio by varying the thickness and diameter of the nanotubes. The control coefficients have been observed to have an impact on the current levels. Increasing the drain control coefficient negatively impacts device performance, while raising the gate control coefficient positively affects the current ratio.

Introduction

The field of semiconductor technology endeavors to minimize the dimensions of transistors and maximize their density on a singular integrated circuit. Nevertheless, the increasing complexity of scaling the average MOSFET has become more challenging due to the reduction of Moore’s law-compliant integrated circuits [1]. As a result, it can be inferred that MOSFET devices will eventually satisfy this fundamental limitation. The recent emergence of carbon nanotubes (CNTs) as a potential replacement for silicon in nanoelectronics has generated significant interest. Their quasi-ballistic properties make them particularly desirable for high-speed applications [2], [3]. The miniaturization of silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) enables several advantages in integrated circuits, including greater packing density, decreased power consumption, and higher switching speed. Integrated circuits’ minimum feature size has decreased dramatically over the course of the last few decades resulting in more transistors than ever before. Leakage currents dramatically rise when the thickness of MOSFETs falls below 1.5 nm, resulting in excessive power consumption and lower device dependability. When the channel length of a MOSFET is less than 10 nm, silicon technology will have reached its limit. For the sake of long-term sustainability, the semiconductor industry is exploring alternative materials and devices that can be included in the present silicon-based technology. Carbon nanotubes (CNTs) are an exciting material among the many possibilities that have been explored. Carbon nanotube field effect transistors have made great strides in understanding device physics and enhancing device performance [4]–[6]. To get over the issues with silicon MOSFETs such as the exponential rise in leakage currents in scaled devices [6]–[8], one of the fundamental concepts is to switch to CNTFETs. By replacing the silicon in a conventional MOSFET channel with a single carbon nanotube, these restrictions may be relaxed, allowing for even more drastic reductions in device size. CNT-based FETs have shown significant improvement over state-of-the-art silicon FETs in recent years. While CNTFETs have excellent device attributes and strong performance, temperature, thickness, and diameter may all have an influence on the device’s actual properties and how well it functions. The characteristics of a CNTFET change gradually when the device’s temperature, diameter, thickness, and control coefficients change. The ON current I_ON and OFF current I_OFF relationship have been studied by varying the following parameters.

CNTFETS Simulation Modelling

The functioning of MOSFETs in the ballistic domain has been investigated using both fundamental analytical models [9]–[12] and in-depth computational simulations [12]–[14]. This work takes into consideration the numerical simulation technique to calculate the mobile charge, the non-equilibrium charge density, and the overall charge formed on the nanotube channel [9], [15], [16]. The aim of this investigation is to assess the efficacy of CNTFET. Within the scope of this inquiry, a capacitance model is used to take into consideration the electrostatics of a CNTFET. In this investigation, we make use of MATLAB to model and simulate the transistor’s ballistic transport.

The determination of current and voltage characteristics begins once the mobile charge and non-equilibrium charge density have been estimated. The next step is to calculate the current-voltage characteristics. Variations in nanotube diameter cause changes in the first sub-band charge, which in turn controls the drain-to-source current at any given drain and gate voltage. Both can be found in the model’s coefficients. In this work, sub-threshold (SS), transconductance (gm), and quantum capacitance (CQ) are examined in relation to gate control coefficients and drain control coefficients [16]–[18]. The equation of drain to source current.

where,

(1) $$\begin{array}{r}{I}_{DS}=\frac{2qkT}{\pi \hslash }[\log (1+e^{\left(\frac{U_{SF}}{kT}\right)})-\log (1+e^{\left(\frac{U_{DF}}{kT}\right)})]\end{array}$$

(2) $$\begin{array}{r}{U}_{SF}=E_{f1}-U_{scf}\mathrm{\&}{U}_{DF}=E_{f2}-U_{scf}\end{array}$$

Assume the reference Fermi level,

(3) $$\begin{array}{r}{E}_{F1}=E_F,E_{F2}=E_F-q{V}_{DS}\end{array}$$

The summation of Laplace potential $\left(U_L\right)$ at the barrier top evaluates self-consistent potential due to three terminal bias voltages and mobile charge depended potential $\left(U_P\right)$. where, ${\mathrm{\alpha }}_G,{\mathrm{\alpha }}_D$ and $\text{represent}{\mathrm{\alpha }}_S$ represents, the gate, drain and source control coefficients respectively.

(4) $$\begin{array}{r}{U}_{scf}=U_L+U_P\end{array}$$

(5) $$\begin{array}{r}{U}_L=-q({\mathrm{\alpha }}_G{V}_G+{\mathrm{\alpha }}_D{V}_D+{\mathrm{\alpha }}_S{V}_S)\end{array}$$

(6) $$\begin{array}{r}{\mathrm{\alpha }}_G=\frac{C_G}{C_{Sum}}{\mathrm{\alpha }}_D=\frac{C_D}{C_{Sum}}{\mathrm{\alpha }}_S=\frac{C_S}{C_{Sum}}\end{array}$$

(7) $$\begin{array}{r}{U}_P=\frac{q^2}{C_{sum}}(N_S+N_D-N_0)\end{array}$$

Here, charge density added by applied voltages,

(8) $$\begin{array}{r}\mathrm{\Delta }N=(N_S+N_D-N_0)\end{array}$$

where $C_G,C_D\text{and}{C}_S$ are the electrostatic capacitances related to gate, drain, and source respectively.

(9) $$\begin{array}{r}{C}_{Sum}=C_G+C_D+C_S\end{array}$$

The ratio of the individual terminal capacitance to the sum of the terminal capacitances can be used to compute the control coefficient.

Result and Discussion

While researching the effectiveness of CNTFETs, it is essential to establish the ratio of the I_ON current to the I_OFF current. When the I_ON/I_OFF ratio is low, switching the output takes more time or results in minor fluctuations, but switching the output quickly while limiting leakage current is possible when the I_ON/I_OFF ratio is high [19]. The I_ON current is determined at V_gs = 0.8 V and V_ds = 0.8 V. The current flowing from the drain to the source while the gate voltage is 0 V is called “off-state current” or “leakage current.” Leakage current lowers a semiconductor device’s efficiency, hence it should be removed or reduced as much as possible.

ION/IOFF Dependency on Gate Control Coefficient

The connection between the gate control coefficient and the I_ON/I_OFF ratio is shown in Fig. 3. In this context, a CNTFET with the chiral vector (13, 0) and thickness and diameter values of 1 nm was taken into consideration. The temperature of 300 K was taken into consideration here. Based on the graph, the I_ON/I_OFF ratio was around 0.96 × 10⁶ when α_G was equal to 0.84, but it climbed to 1.25 × 10⁶ when the value of the gate coefficient was raised to 0.99. As a result, the device’s performance has significantly increased, and the current ratio has increased by almost 1.3 times.

Fig. 1. Proposed CNTFET model.

Fig. 2. Proposed 2D capacitor model of CNTFET.

Fig. 3. α_G vs I_ON/I_OFF.

Effect of Diameter

The connection between the Gate control coefficient (α_G) and the I_ON/I_OFF ratio is seen in Fig. 4. Similar CNTFETs as previously mentioned with the chirality (13, 0) were employed in this experiment, and the gate oxide that was used was hafnium oxide, which has a dielectric constant of 25. Throughout the process of data collection, the diameter of the nanotubes was adjusted from 1 nm to 5 nm, while the thickness remained constant at 1 nm. The value of the gate control coefficient was adjusted from 0.83 to 0.98 for the purpose of data analysis. It can be seen rather clearly from the findings that raising the gate control coefficient leads to a rise in the current ratio for all diameters that is essentially linear, which implies that greater current is associated with improved device performance. Increasing the diameter, on the other hand, leads to an increase in the total current ratio. This is because even if the saturation current increases as the diameter increases, the leakage current increases owing to the fact that the diameter is inversely proportional (1) to the band gap [17]. This is the reason why this occurs.

Fig. 4. α_G vs I_ON/I_OFF varying diameter.

where E_G represents the energy difference between the valance and conduction band of the CNT, $a_{cc}=a$ distance of two nearing carbon-carbon bonding, and the $D_{CNT}$ stands for the diameter of the carbon nanotube. For example, when the gate control coefficient is 0.84 for a 1 nm diameter the I_ON/I_OFF ratio is about 9.5 × 10⁶ but at the same coefficient value for a 5 nm diameter the current ratio increased about 18.42%. So, a higher diameter with higher gate control coefficient results in the higher optimized device.

(10) $$\begin{array}{r}{E}_G=\frac{2a_{CC}(V_{CC})}{D_{CNT}}\end{array}$$

Effect of Thickness

The I_ON/I_OFF ratio was measured using the same kind of CNTFET with varying gate control coefficient that was used in the previous example (see Fig. 5). In this case, however, the diameter was held constant at 1 nm while the thicknesses varied from 1 nm to 3 nm to 5 nm. As in Fig. 3, when an increase in the value of the gate control coefficient, the I_ON/I_OFF ratio improves, leading to a more effective device. By comparing the diameter to the thickness, however, the reverse is seen. That is, the I_ON/I_OFF ratio increases with decreasing thickness, leading to a significant on-state current. This is because the off-state current is reduced due to improved gate voltage management of the channel. The results matched those found in the cited works [20], [21]. Taking the I_ON/I_OFF ratio as an example: at 1nm thickness with a gate control coefficient value of 0.93, it is 11.5 × 10⁶, while at 5nm thickness, it is only around 9.25 × 10⁶. Hence, improved device performance may be achieved by trading low thickness for a larger gate control coefficient.

Fig. 5. α_G vs I_ON/I_OFF varying thickness.

ION/IOFF Dependency on Drain Control Coefficient

Fig. 6 shows the I_ON/I_OFF ratio’s correlation with the drain control coefficient. The data was collected assuming a chiral vector (13, 0) CNTFET with a thickness and diameter of 1nm. Here, a temperature of 300 K was taken into consideration. Values between 0.005 and 0.30 were tested for the drain control coefficient. The decrease in the I_ON/I_OFF ratio that occurs with raising the drain control coefficient is graphically shown in the graph. This is because there is an exponential rise in the leakage current after the value of 0.08 [22]. The graph shows that the I_ON/I_OFF ratio was 6.9 × 10⁶ when D = 0.05 but drops to practically nil when the drain control coefficient value is raised to 0.30, indicating a drastic decrease in the device’s performance and current handling capacity.

Fig. 6. α_D vs I_ON/I_OFF.

Effect of Diameter

The drain control coefficient varies as a function of the I_ON/I_OFF ratio, as seen in Fig. 7. Here, a CNTFET like the one in Fig. 6 was under consideration. Here, however, the thickness was held constant at 1 nm in order to focus on the impact of diameter, which was altered from 1 nm to 5 nm. Hafnium oxide (€_r = 25) was studied for use as a gate oxide. Like the previous graph, the results show that raising the drain coefficient decreases the I_ON/I_OFF ratio, as the leakage current (I_OFF) might rise dramatically with further increases in the drain control coefficient. Since a more considerable saturation current occurs from a larger diameter, the influence of diameter is obvious at a lower drain control coefficient value, where a higher diameter results in a higher current ratio. Yet, due to the diameter’s inverse relationship with the band gap (1), the leakage current becomes larger [17].

Fig. 7. α_D vs I_ON/I_OFF varying diameter.

Effect of Thickness

Fig. 8 shows a plot of the drain control coefficient vs the I_ON/I_OFF ratio for CNTTFETs of varying thicknesses. The diameter was fixed at 1 nm, and the temperature was maintained at 300 K. A greater α_D value leads to a lower I_ON/I_OFF ratio, which indicates a decline in the device’s performance, as seen in Figs. 6 and 7. In the case of thickness, a lower value suggests better gate voltage control of the channel because of an optimum current ratio.

Fig. 8. α_D vs I_ON/I_OFF varying thickness.

Conclusion

By altering the CNTFET’s width and thickness, the authors of this work were able to conduct an in-depth investigation of the relationship between the gate control coefficient and the drain control coefficient, as well as the I_ON/I_OFF ratio. According to the findings, a greater gate control coefficient leads to an optimal current ratio; however, when the drain control coefficient is increased, the I_ON/I_OFF ratio drops close to zero, which leads to a decline in device performance. The impact of thickness has the opposite relationship to that of diameter. When it comes to CNTFETs, a larger diameter results in a greater I_ON/I_OFF ratio, but a larger thickness result in a lower current ratio. Hence, a greater gate control coefficient combined with a larger diameter and a thinner layer result in the best possible performance.